USR-ES1 is embedded with W5500 Wizard chip and uses hardware logic gate circuit to implement the transport layer and network layer of TCP/IP protocols (such as TCP, UDP, ICMP, IPv4 ARP, IGMP, PPPoE and other protocols) and integrates a physical layer data link layer and 32K on-chip cache RAM. Bytes for sending and receiving data This makes the host computer's main control chip only need to perform TCP/IP application-level control data processing. This saves the host computer's workload for data simulation, protocol processing, and processing interrupts. and improve system usability and reliability.
During use, users can use W5500 is an MCU peripheral RAM, which is very simple. The external interface of W5500 is a
general 80MHz high-speed SPI, which can be selected for different platforms to expand the high-speed Ethernet solution. Auto-negotiation status shows that the SPI interface is fast and stable.
Dimensions and pins are compatible with Wiznet's official WIZ820io module.